Experimental Demonstration of 100nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications

Vertical In0.53Ga0.47As tunnel field effect transistors (TFETs) with 100nm channel length and highk/metal gate stack are demonstrated with high Ion/Ioff ratio (>10). At VDS = 0.75V, a record on-current of 20μA/μm is achieved due to higher tunneling rate in narrow tunnel gap In0.53Ga0.47As. The TFETs exhibit gate bias dependent NDR characteristics at room temperature under forward bias confirming band to band tunneling. The measured data are in excellent agreement with two-dimensional numerical simulation at all drain biases. A novel 6T TFET SRAM cell using virtual ground assist is demonstrated despite the asymmetric source/drain configuration of TFETs. Introduction: Inter-band tunnel FETs (TFETs) with a gatemodulated Zener tunnel junction at the source are of interest for MOSFET replacement since the reverse biased tunnel junction in the former eliminates the high-energy tail of the Fermi distribution of valence band electrons in the source region thereby allowing for abrupt turn-on near the OFF state. However, till date, almost all Si and SixGe1-x based TFETs exhibit low Ion due to high tunnel barrier. We present here improved Ion and Ion-Ioff ratios utilizing a vertical In0.53Ga0.47As TFET. A fundamental advantage of the vertical transistor design is that high quality, in-situ doped junctions are realized enabling not only observation of room temperature NDR effects but also reduction of off-state reverse biased p+/i/n+ leakage. Device Fabrication: N-channel In0.53Ga0.47As TFETs were fabricated using MBE grown epitaxial structure on semiinsulating InP substrate. The epitaxial layers comprise of 300nm thick n+ drain region (Si doping of 5x10 cm), 100nm intrinsic channel region and 60nm thick p+ source region (C doping of 1x10 cm) (Fig. 1a). After source metal (Ti/Pt/Au) evaporation and lift-off, a facet dependent mesa sidewall etch is performed using citric acid and peroxide chemistry exposing the n+ region (Fig. 1b). A highly conformal 10nm thick Al2O3 is deposited on the mesa sidewall using atomic layer deposition (ALD) followed by gate metallization (Pt/Au) and liftoff (Figs. 1cd). A subsequent lithography step defines source/drain contact openings and the Al2O3 film is removed thereof to make direct contact to the source/drain regions, followed by a final isolation etch (Fig. 1e). Figs. 1g-h show the SEM images of fabricated In0.53Ga0.47As vertical TFET featuring gate air-bridge and conformal gate stack on the sidewall. Device Results and Discussion: Figs. 2(a)-(b) show the measured transfer and output characteristics of the 100nm channel length tunnel transistors at room temperature. The minimum current (“leakage floor”) at VDS = 50mV is only 40 pA/μm increasing to 6nA/μm at VDS = 0.75V. The corresponding on currents are 0.5μA/μm (linear) and 20μA/μm (saturation). This translates to Ion-Ioff ratio of ~ 10 4 and 3x10, respectively. Two distinct regions of operation are evident from the output characteristics – a reverse biased zener diode and a forward biased Esaki diode as a function of the gate voltage. Fig. 3 shows the 2 terminal characteristics of non-gated In0.53Ga0.47As p+/i/n+ diodes fabricated at the same time showing excellent agreement with the modeled data at various temperature. At low reverse bias, SRH generation-recombination dominates the J-V while, at high reverse bias, it is direct band-to-band tunneling. We employed a commercial two dimensional numerical simulator solving non local tunneling selfconsistently with the device electrostatics to model the measured TFET transfer characteristics at 50mV/0.75V VDS (Fig. 4). The leakage floor agrees with the experimental and modeled reverse biased p+/i/n+ diode J-V and the oncurrent agrees well with the non-local band to band tunneling model. Fig. 4 shows the impact of Dit (extracted from the C-V and G-V measurements on control In0.53Ga0.47As MOSFETs (Fig. 5a-d)) on the In0.53Ga0.47As TFET turn-on characteristics. While Dit effect on steep switching is negligible due to the limited movement of Fermi level near the channel conduction band edge, trap assisted tunneling (TAT) and subsequent thermal emission has strong effect on TFET turn-on (Fig. 6a,b). Temperature dependent measurement of In0.53Ga0.47As TFET shows that the leakage floor increases exponentially with temperature (SRH) (Fig. 7) whereas Ion (a) increases at low VGS due to gap reduction (limited by tunnel barrier resistance) b) decreases with temperature at high VGS due to phonon scattering (limited by channel resistance) (Fig. 8). Gated negative differential resistance (NDR) behavior in TFET output characteristics during drain-to-source forward bias operation confirm the inter-band tunneling process (Fig. 9). Logic and SRAM Performance: Fig. 10 shows 100nm In0.53Ga0.47As TFET (this work) outperforming previously reported Si, Si0.3Ge0.7 , unstrained and strained Ge TFETs (of comparable gate length) with the highest on current performance till date and projects its logic performance with EOT scaling and increasing indium content. Due to its inherent asymmetric source and drain design, bidirectional current conduction is not possible in TFETs as shown with In0.53Ga0.47As and Si TFETs (Fig. 11). This makes TFET based pass transistor implementation impossible resulting in 6T TFET SRAM with degraded read or write margins (Fig. 12).7T and 8T TFET SRAM implementations with separate read and write port have been proposed compromising cell size. We implement a novel 6T TFET SRAM where inward M5 and outward M6 TFETs are used to write “1” and “0”, respectively, at the same node Q (Fig. 13). During writing, the cell is weakened by disabling the inverter pair crosscoupling via virtual ground. Excellent read and write noise margins are achieved in this 6T TFET SRAM (Fig.14). Conclusion: We have demonstrated 100nm LG vertical In0.53Ga0.47As TFET with 10 4 Ion-Ioff ratio and 20μA/um on current. The TFET I-V characteristics are explained by nonlocal inter-band tunneling, SRH and TAT. A 6T SRAM cell is shown with excellent noise margin down to 0.3V supply voltage making narrow gap III-V TFET a promising device architecture for ultra low power digital applications. Fig 1. (a) MBE grown In0.53Ga0.47As p+/i/n+ eptitaxial structure; Process Fabrication flow: (b) Source contact lithography, Ti/Pt/Au metallization and liftoff followed by sidewall mesa patterning using citric acid based wet etch chemistry; (c) Native oxide removal on the sidewall followed by ALD deposition of 10nm thick Al2O3 dielectric at 300 C (d) Gate patterning, Pt/Au metallization and liftoff; (e) S/D contact patterning, wet etch removal of Al2O3 ; (f) Ti/Pt/Au metallization and liftoff and a final mesa isolation etch; (g) Tilted view SEM picture of fabricated vertical TFET featuring a gate air-bridge process (h) Cross-section SEM picture of the etched sidewall with conformal gate stack. Gate Gated Sidewall Drain 11) 10nm Alumina In0.53Ga0.47As (100) 100 nm Pt/Au